The present invention relates generally to computer processing and memory, and more particularly to power management for in memory computing.
Computer systems often require a considerable amount of high speed memory, such as random access memory (RAM), to hold information (e.g., data and programs) when a computer is powered and operational. Memory device demands have continued to grow as computer systems have increased in performance and complexity. As devices increase in complexity, managing power used by processing units, such as cores, is an important factor in overall computing performance. In a system with multiple processing units, a first processing unit may consume power while waiting on a result from second processing unit, where the second processing unit may not perform at an optimal speed due to its need for more power.